1.Placed in parallel with a voltage source, they limit current to a device. In series with a voltage source they make up a voltage divider.
1.電阻與電源并聯(lián)連接,則電阻限定流入裝置的電流.電阻與電源串聯(lián),則電阻便成為電壓分壓器.

2.The fifth band, when present, indicates the failure rate (in percentage) per 1000 hours of service. This is sometimes called the reliability factors.
2.第五條色帶,當(dāng)其出現(xiàn),表示每使用1000小時(shí)的故障率(用百分比表示).它有時(shí)也被稱為可靠性因子。

3.Why is skew important? In high-speed systems, clock skew forms an important component of timing margin. A skew of 1 ns is a significant portion of a 15-ns cycle time. If the timing budget does not allow for skew, it is highly likely that the system will perform unreliably.
3.為什么偏移這么重要？在高速系統(tǒng)中，時(shí)鐘偏移是時(shí)序富裕量的重要組成部分。在一個(gè)以15納秒為周期的時(shí)間里，1納秒的偏移都是很顯著的部分。如果時(shí)序預(yù)算不允許偏移，系統(tǒng)很可能無法穩(wěn)定運(yùn)行。

4.In today's designs, with clock rates over 100 MHz and rise times commonly 1 nanosecond (ns) or less, designers cannot ignore the role interconnections play in a logic design.
4.在當(dāng)今的設(shè)計(jì)中，時(shí)鐘速率都超過了100MHz，并且上升沿通常只有1納秒或者更少，設(shè)計(jì)者不能忽視在邏輯設(shè)計(jì)中互連的重要性。

5.The faster clock rates and rise times increase both capacitive and inductive coupling effects, which makes cross talk problems greater. They also mean shorter time for reflections to decay before the data is clocked and read, which decreases the maximum line length that can be used for unterminated systems.
5.更快的時(shí)鐘速率和上升沿都將增加電容耦合及電感耦合效應(yīng)，這使得串?dāng)_問題更加嚴(yán)重。這也意味著在數(shù)據(jù)被寫入和讀取之前的反射衰減時(shí)間更短，它減少了無終端系統(tǒng)中最大的可用線路長(zhǎng)度。